A non-memory semiconductor market accounts for about 78% of the global semiconductor market and continues growing. Unlike memory semiconductors subject to frequent fluctuations in price, non-memory semiconductors are less subject to fluctuation in price and are high value-added products. However, the non-memory semiconductors are manufactured by high-level techniques. Thus, until now, Korean manufacturers have intensively fostered the memory semiconductor industry capable of mass production in small variety with relatively lower-level techniques. Accordingly, Korea's memory manufacturing techniques are among the highest level in the world and Korean memory semiconductors account for about 40% or more of the global memory semiconductor market. However, the memory semiconductor market is already saturated and the price has dropped. This means that the Korean manufacturers should advance into a new business area. Therefore, an advance into the non-memory semiconductor market is important to the Korean manufacturers for securing competitiveness in the global semiconductor market.
In manufacturing a non-memory semiconductor device, a wiring process is most important. As a semiconductor device has been highly integrated with higher speed and a multilayer interconnecting process has been miniaturized, a line width in wiring has been rapidly decreased. However, a decrease in line width in wiring within an ultra large scale integrated circuit semiconductor device causes a signal delay (RC delay) depending on an electrostatic capacitance (C) between metal wires and a resistance (R) of wiring metal and a decrease in operation speed of the entire device. Actually, when a semiconductor device of 130 nm or less is manufactured with existing aluminum and an insulating material such as a silicon oxide (SiO2) film, there is a decrease in data processing speed due to resistivity of the aluminum and a high dielectric constant of the oxide film. For this reason, a study on Cu/low-k integration using copper having a high electric conductivity for wiring and using a low-k material as an insulating material has been carried out. As for a logic device of 90 nm being produced in large quantities, Cu/low-k material has been used instead of Al/SiO2. As a Cu wiring process has been performed with higher density, an ultra low-k material to be used for devices of 50 nm or less and 40 nm or less needs to be developed.
A low-k material has been used as an interlayer insulating material for the last several years and contributed to development in the semiconductor industry. However, due to high integration with high speed continuously required for a semiconductor device, there has been a demand for a development of a new material which can be substituted for the existing low-k material and has a lower dielectric constant. A nanoporous ultra-low dielectric material has been expected as a new material, but has weak mechanical and electrical properties due to pores for reducing a dielectric constant.